With HSE = 25 MHz, the PLL configuration must satisfy:

• SYSCLK = 100 MHz: VCO / PLL_P = 100 MHz.
• USB = 48 MHz: VCO / PLL_Q = 48 MHz.
• PLL Input: HSE / PLL_M = 1 MHz (typical for stability, 1-2 MHz allowed).
• VCO Constraints: 100-432 MHz (per STM32F411 datasheet).

Let’s try the main PLL:

• PLL_M = 25 (25 MHz / 25 = 1 MHz).
• For SYSCLK = 100 MHz, VCO = 200 MHz (PLL_N = 200, PLL_P = 2).
• For USB = 48 MHz, VCO / PLL_Q = 48 MHz → PLL_Q = 200 / 48 = 4.166 (not an integer).

Since PLL_Q must be an integer (4-15), 48 MHz USB is not possible with VCO = 200 MHz:

• PLL_Q = 4 → 200 / 4 = 50 MHz (as you noted, incorrect for USB).
• PLL_Q = 5 → 200 / 5 = 40 MHz (also incorrect).

To get exactly 48 MHz:

• VCO must be a multiple of 48 MHz (e.g., 192 MHz or 240 MHz).
• For VCO = 192 MHz: PLL_N = 192, PLL_P = 2 → SYSCLK = 96 MHz, PLL_Q = 4 → USB = 48 MHz.
• For VCO = 240 MHz: PLL_N = 240, PLL_P = 2 → SYSCLK = 120 MHz (exceeds 100 MHz limit), PLL_Q = 5 → USB = 48 MHz.

Since SYSCLK cannot exceed 100 MHz, VCO = 192 MHz (SYSCLK = 96 MHz, USB = 48 MHz) is the closest using the main PLL.

2025/08/03 by admin