Change qemu to use 16M ram for xv6-riscv

2022-10-30 1.5K

After testing, the minimal memory of xv6-riscv needed is 3MB

start point to build our own jtag for our risc-v cpu

2022-02-13 2.1K

After days of hacking, i finally found out there is a dummy driver in openocd. just ./configure --enable-dummy and run…

Our RISC-V simulator interface

2020-10-29 2.8K

Hacking Lattice toolchain lesson 1

2019-11-27 3.4K

Lattice Diamond use these commands to compile my project into jed file Synthesize Design: synthesis -f ControlLed_impl1_lattice.synproj -gui -msgset C:/workspace/fpga/ControlLed/promote.xml…

Can write simple test bench in vivado

2018-02-02 3.8K

After reading my verilog book for few days, i can write test bench file to test my verilog program in…

For the user interface, Vivado is much nicer than Quartus

2018-01-27 4.3K

For the user interface, Vivado is much nicer than Quartus. Better to stick into Xilinux to build my soft core.